1. Field of the Invention
The present invention relates to testing of semiconductor devices, and more particularly, to a parallel test circuit for simultaneously testing multiple memory cells in a semiconductor memory device.
2. Related Art
Typically, a plurality of identical integrated circuit (IC) memory devices, each comprising a number of memory cells, are fabricated simultaneously on a semiconductor wafer. The wafer is then separated, typically by sawing or breaking, into individual devices, or "chips," which are then individually packaged for subsequent use.
Typically, each memory device includes a built-in test circuit fabricated on the wafer along with the device to test its operation. Memory devices are generally tested at least twice. A first test at the wafer level detects defective memory cells by connecting detection probes to input/output terminals of the test circuit on the wafer. Defective chips may be discarded, or in some cases, repaired on the wafer.
After the devices have been tested at the wafer-level, they are separated from the wafer, and those passing the first test are incorporated into suitable IC packages, each containing an individual memory device. A second, package-level test is then performed on the packaged devices to determine whether their electrical performance falls within specification. In this test, test signals are applied to the devices through the input pins of the packages, which are connected internally to the input/output pads of the test circuit.
Both the wafer-level and the package-level tests typically employ a "parallel" test method which tests a number of memory cells simultaneously. This procedure is well known in the art, and is described in detail in the book, Semiconductor Memories: A Handbook of Design, Manufacture, and Application, 2nd Ed., by Betty Prince; John Wiley & Sons, pp. 698-717, 1991.
There are various ways to reduce the production cost of memory devices. One way is to reduce device testing time, which can be achieved by testing several memory cells simultaneously. Referring to FIG. 1, a conventional parallel test circuit includes a parallel test control circuit 100 and four data input buffers 120, 140, 160 and 180 adapted to receive and write 4-bit input data into a memory cell array of a semiconductor memory device (not shown) in response to a chip select (CS) signal. The test control circuit 100 is connected to a parallel test pad 1, and the four data input buffers 120, 140, 160 and 180 are connected to respective data input pads 2, 3, 4 and 5. The control circuit 100 controls the data input buffers 120, 140, 160 and 180 such that, in response to the application of a "test active" signal MDQ to parallel test pad 1, a "write data" input signal DQ1 of a given level applied to any one of data input pads 2, 3, 4 and 5 alone will generate output data D1, D2, D3 and D4 of an identical level at the outputs of data input buffers 120, 140, 160 and 180, respectively.
More specifically, in the conventional parallel test and test circuit of FIG. 1, an input signal DQ1 of a given level is applied to any one (for example, pad 2) of data input pads 2, 3, 4 and 5, and the other pads 3, 4 and 5 are left "floating." In this state, if a test active signal MDQ of a high level is applied to parallel test pad 1, then a low level signal will be applied through the inverters 10, 11 and 12 to one of the input terminals of each of the four NAND gates 17, 21, 25 and 29. Thus, even though data input pads 3, 4 and 5 are floating, the outputs of the NAND gates 17, 21, 25 and 29 will all be at a high level. Therefore, the level of the test input signal DQ1 applied to data input pad 2 determines the output of NAND gate 14, and since this output level is sent as an input to the NAND gates 18, 22, 26 and 30, the outputs D1, D2, D3 and D4 of NAND gates 18, 22, 26 and 30, respectively, will have the same level as that of the buffer 120 in response to the test input to data input pad 2. This parallel test is thus capable of checking the write operation of all four data input pads 2, 3, 4 and 5 at the same time by inputting write data DQ1 to only one data input pad 2, thereby reducing the time required to test all of the pads when tested one at a time.
However, it may also be noted that, while such a parallel test can also simultaneously check the current leakage of the data input buffer 120 associated with the data input pad 2, it cannot simultaneously test the current leakage of the other data input buffers 140, 160 and 180 associated with input pads 3, 4 and 5, respectively, due to the fact that the latter pads are floating. Therefore, in order to check the current leakage of each of these other data input pads and buffers, a separate, additional current leakage test must be performed on each pad, which somewhat offsets the economy achieved by the parallel data writing test of the memory cells described above.
It is therefore desirable to be able to test both the write operation and the current leakage of the data input pads and buffers simultaneously and in parallel.